The present invention relates to transistor design, and, in particular, a thermal nitrogen deposition method to improve the uniformity of the nitrided layer of a gate capacitor of a transistor.
The speed requirements for high-performance 0.13 um CMOS devices has driven gate oxide thicknesses to less than 20 xc3x85, with inversion and physical thicknesses trending to less than 20 xc3x85. As the dielectric layers are scaled thinner, the leakage currents through these gates exponentially increase due to more direct tunneling of electrons and holes through the potential barriers of the dielectric. This can affect device properties by causing higher standby power consumption, reliability problems, and degradation of certain chip functions such as timing. Battery powered devices for mobile applications for example, have some of the strictest requirements for leakage current, where lower leakage currents produce longer battery life.
FIG. 1 shows a transistor structure with the gate dielectric (20). Gate leakage current is defined as the current from gate to drain when Vg (22) is less, than the threshold voltage of the device. This current is an exponential function of thickness, with the current increasing by 2-3xc3x97 for every 1 xc3x85 decrease in thickness, in the sub-20 xc3x85 thickness range for a gate dielectric layer that is formed using SiO2.
Remote plasma nitridation (RPN) or decoupled plasma nitridation (DPN) are methods used to introduce large concentrations of nitrogen into the gate dielectric layer, thereby forming a silicon oxynitride gate dielectric. With the incorporation of nitrogen, the gate leakage current can by reduced. This is mainly due to increasing the capacitance of the layer which allows for larger physical thicknesses with the same electrical thickness. There is also some reduction in leakage current due to the change in chemical bonding at the dielectric-Si substrate interface. These particular processes are desirable due to their ability to incorporate large concentrations of nitrogen ( greater than 4xc3x971021 at/cm3) and their ability to control the profile of the nitrogen throughout the dielectric layer. These process techniques however, can be inherently non-uniform, thus causing a large non-uniformity of device parameters across the wafer. Non-uniformity of device parameters can cause severe yield degradation in chip performance if certain specifications are out of range. These electrical parameters can include leakage current, electrical thickness, threshold voltage, and device current. This invention addresses this non-uniformity, and demonstrates that the physical thickness and nitrogen concentration is improved by making use of the techniques described in the invention.
The present invention relates to a method for improving the uniformity of the nitrided layer that is formed over the base SiO2 layer of a transistor gate dielectric, thus lowering the leakage current through the base SiO2 layer.